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| introduction the minimization of the power drawn from the mains under light load conditions (standby, suspend or some other idle mode) is an issue that is recently becoming of great interest, above all else because new and more severe standards are coming into force. this is already well-established in the area of computer monitors, where norms define precisely the vari- ous idle modes and the relevant maximum consumption admitted, but more and more often power sup- plies for other pieces of office equipment (i.e. printers, photocopiers, fax machines, ac-dc adaptors, etc.), are required to accomplish with specifications concerning energy saving. anyway, minimizing the power wasted by a lightly loaded switch-mode converter is a demanding chal- lenge for power supply designers and, to achieve the goal, an appropriate design strategy is required. march 2000 ? AN1049 application note minimize power losses of lightly loaded flyback converters with the l5991 pwm controller by claudio adragna the l5991 pwm controller is particularly suitable for smps of equipment that must comply with standards concerning energy saving. the device, optimized for flyback topology, monitors the power demanded by the load and changes the operating frequency of the converter accordingly: high fre- quency at heavy load, low frequency at light load. in this way, power losses dependent on frequency are reduced at light load maintaining, at the same time, the advantages offered by a high switching frequency at heavy load. the frequency reduction is very helpful but is not the only means needed to minimize power losses. this note surveys the above mentioned functionality of the l5991 (called ostandbyo function) as well as the most significant points to consider in order to achieve the goal of a very efficient lightly loaded flyback. + - timing 2 3 + - 14 t vref clk 2.5v + - 1.2v 13 blanking pwm fault soft-start r sq 21v 10v vref ok dis + - e/a 1v r 2r dis 2.5v 7 6 5 11 10 9 4 8 15 1 17v + - pwm uv lo 12 sgnd c omp ss is en dis dc rct sync d c-lim v cc vref vfb pgnd out v c over c urrent 16 st-by vref standby + - standby 2.5/4.0v figure 1. l5991 internal block diagram 1/24
the key point of this strategy is a low switching frequency. it is well-known that many of the power loss sources in a lightly loaded flyback waste energy proportionally to the switching frequency, hence this should be reduced as much as possible. on the other hand, it is equally well-known that a low switching frequency leads to bigger and heavier magnetics and makes filtering more troublesome. it is then desirable to make the system operate at high frequency under nominal load condition and to reduce the frequency when the system works in a low-consumption mode. this requires a special func- tionality of the controller: it should be able to recognize automatically the condition of light or heavy load and should adequate its operating frequency accordingly. the l5991 pwm controller, with its ostandby functiono, meets exactly this requirement. the function is optimized for flyback topology: in fact, power supply of office equipment lies most often in the medium- low power range, where flyback topology features the lowest cost/performance ratio and is, therefore, the favorite one. however, the goal of power losses minimization cannot be achieved with only a simple reduction of the switching frequency. although the most important, this is only one of the numerous points of a wide- ranging strategy that must be looked into on the whole. this application note is composed of two distinct parts. the first part deals with the l5991, describes the operation of the ostandby functiono in detail and states several relationships useful for the design. the second one provides an overview of the points to be considered in the above mentioned strategy, as well as a number of tips that can be helpful. 1) designing with the l5991 pwm controller the l5991 the device, whose internal block diagram is shown in fig. 1, is based on a standard opeako current mode pwm controller, such as the uc384x family, with the addition of numerous ancillary features among which standby function is the most noticeable. the l5991, which is available in dip16 and so16n packages, features the following characteristics: very low start-up current (75 m a typ. - 120 m a max.) ; low quiescent current (7 ma typ. - 10 ma max.) ; internal reference with 1% precision guaranteed (@ tj=25 c); high current capability, large bandwidth, high slew-rate error amplifier; high-speed current loop (< 100 ns delay to output); high current capability totem-pole output for mosfet or igbt drive; standby function ; in/out synchronization; precise maximum duty cycle control; programmable soft-start 100 ns leading edge blanking on current sense for increased noise immunity; overcurrent protection with soft-start intervention; latched disable function; all these characteristics are described in detail in the datasheet of the device. in this context, however, it is worth emphasizing the low current consumption of the device, both before start-up and when running. along with the standby function, the low consumption turns out to be particularly useful for minimizing losses. table 1 compares these characteristics with the uc384xa/b family. table 1. l5991 vs. uc384xa/b family controller start-up current quiescent current standby function l5991 75 m a typ. 120 m a max. 7.0ma typ. 10.0ma max. yes uc384xa/b 300 m a typ. 500 m a max. 12ma typ. 17ma max. no AN1049 application note 2/24 the l5991 can be used in off-line smps' with any single-ended topology. however, its features make the device particularly useful for power supplies based on flyback topology for office equipment that must comply with standards concerning energy saving. monitor displays, printers, photocopiers, scan- ners and fax machines are the most noticeable examples. standby function description the l5991 automatically detects a light load condition for the converter and decreases the oscillator frequency on that occurrence. the nor- mal (higher) oscillation frequency is automat- ically resumed when the output load builds up and exceeds a defined threshold. this function- ality is called ostandby functiono. like in every opeako current mode controller, the output voltage (v comp ) of the error amplifier (e/a) of the device moves depending on the power drawn from the mains (see appendix opeak current mode control basicso). the basic principle of the standby is then monitoring the e/a output . if the peak primary current decreases as a result of a decrease of the power demanded by the load v comp will decrease as well. if this falls below a fixed threshold (v t1 ), the oscillator, which was working at f osc , will be forced to work at a lower value (f sb ). the frequency drop, however, implies a sudden in- crease of the peak primary current and, therefore, of v comp . some hysteresis will be necessary to pre- vent the frequency from switching back to f osc . in fact, v comp will have to exceed a second threshold (v t2 >v t1 ) in order for the oscillator frequency to be reset at f osc . the hysteresis (v t2 -v t1 ) will be large enough to prevent the above mentioned undesired phenomenon. this operation is shown in fig. 2. fig. 3 shows how the function is implemented internally. only one pin (st-by, 16) is required and is used to connect an external resistor (r b ) to the oscillator pin (rct, 2). in this way, both the normal and the standby frequency are externally programmable. the capacitor c t and the resistor r b , along with r a , set the operating frequency of the oscillator in nor- mal operation (fosc). in fact, as long as the standby signal is high, the pin is internally connected to the reference voltage vref by a n-channel fet (see fig. 3), thus the timing capacitor c t is charged through r a and r b . when the standby signal goes low the n-channel fet is turned off and the pin becomes floating. r b is now disconnected and c t is charged through r a only. in this way the oscillator frequency (f sb ) will be lower. the oscillation frequency can be estimated with the following approximate relationships: f osc 1 c t ? ( 0.693 ? ( r a M M r b )+ k t ) (1), 1234 vcomp pin f osc f sb stand-by normal operat ion v t 1 p no p sb v t 2 figure 2.standby function dynamic operation. - + - + 2.5 2.5/4 66k w r standby 10v level shift comp fb vref st-by 4 16 6 rct c t r a r b 2 5 low high standby d97in752a v t1 2.6v v t2 4v v comp - + isen 13 r driver cut standby block 2r figure 3. standby function internal schematic and operation AN1049 application note 3/24 which gives the normal operating frequency, and: f sb 1 c t ? ( 0.693 ? r a + k t ) (2) which gives the standby operating frequency, that is the one the converter will operate at when lightly loaded. in the above expressions, r a // r b means: r a M M r b = r a ? r b r a + r b (3), and k t , defined as: k t = ? ? ? 90, v 15 = vref 160, v 15 = gnd/open (4) is related to the duration of the falling-edge of the sawtooth. in case v15 is connected to vref, how- ever, the switching frequency will be a half the values resulting from (1) and (2). fig.3 shows also the comparator with hysteresis that recognizes the load condition of the converter. the thresholds v t1 and v t2 are internally fixed at 2.5 v and 4 v respectively (typical values). with reference to fig. a1 in appendix, the peak voltages on the current sense pin of the l5991 (isen, 13) relevant to v t1 and v t2 are: v cspk1 = v t1 - 2 ? v f 3 = 2.5 - 2 ? 0.7 3 = 0.367v (5) v cspk2 = v t2 - 2 ? v f 3 = 4.0 - 2 ? 0.7 3 = 0.867v (6). it is more convenient to refer to the thresholds v cspk1 and v cspk2 (rather than v t1 and v t2 ), because they can be immediately related to the peak input current. although having fixed thresholds may seem a lack of flexibility, in reality it is possible to adjust the thresholds in terms of input power level, if needed, by adding a dc offset voltage (v o ) on the current sense pin. standby operation analysis in this context, flyback converters are classified as stated in the appendix oflyback basicso. another as- sumption is that the delay to output of the l5991 is compensated, thus the offset voltage vo is intended as the amount exceeding the value needed for compensation (see appendix opeak current mode control basicso). this analysis does not take other non-idealities into consideration, thus the results are approxi- mate. please refer to the appendix for an explanation of symbols, terminology and formulas. when v comp =v t1 , that is on the boundary of the standby mode, the peak input current is equal to: i ppk1 = v cspk1 - v o r s = 0.367 - v o r s (7), corresponding to the standby input power which, under the assumption of dcm (discontinuous conduc- tion mode) operation, can be expressed as: p insb = 1 2 ? l p ? f osc ? ? ? ? 0.367 - v o r s ? ? ? 2 (8). the standby power can be expressed also in terms of the maximum input power (p inmax ). this is set by the sense resistor r s , which is selected so as to limit the peak primary current at the value (i ppkmax ) rele- vant to p inmax : r s = 1 - v o i ppkmax =( 1 - v o ) ? ````` ` l p ? f osc 2 ? p inmax (9). AN1049 application note 4/24 by substituting (9) in (8) it is possible to obtain: p insb = p inmax ? ? ? ? 0.367 - v o 1 - v o ? ? ? 2 (10). the frequency change f osc ? f sb pushes flyback into a deeper dcm operation and causes a sudden in- crease of the peak primary current (since the input power does not change). as a result, the peak volt- age on current sense will jump from v cspk1 to: v cspk1 ' = v o + r s ? ```` ` 2 ? p sb l p ? f sb = v o +( 1 - v o ) ? ```` p sb p inmax ? ``` f osc f sb (11). this value must be if the sense resistor r s is selected as follows: r s = 1 - v o i ppkmax = 1 - v o p inmax v emin + v emin 2 ? z e (17). (with z e evaluated at f sw =f osc ), the peak voltage on the current sense pin at transition will be given by: v cspkt = v o +( 1 - v o ) ? v e v emin ? 2 ? p int p inmax + p intmin (18), (with p int and p intmin evaluated at f sw =f osc ). it will assume its minimum value at minimum mains volt- age (that is, @ v e =v emin ? p int =p intmin ): v cspktmin = v o +( 1 - v o ) ? 2 1 + p inmax p intmin (19). table a2 in appendix shows that in mcm systems (for which p intmin p inmax p intmax ) the ratio p intmax / p intmin does not exceed 3.31 in practical cases. this means that also p inmax /p intmin will not exceed 3.31. as a result, the transition from ccm to dcm will occur at v cspk values that do not exceed 2 / (1+3.31) = 464 mv (when v o = 0, and even larger values when v o > 0). in the end, since v cspk1 = 367 mv, when the l5991 activates the standby frequency mcm systems are operating in dcm. the standby input power will then be found once more from equation (8) which, ac- counting for (17) and after some manipulations, yields: p insb p inmax = 1 4 ? ? ? ? 0.367 - v o 1 - v o ? ? ? 2 ? ? ? ? 1 + p inmax p intmin ? ? ? 2 ? p intmin p inmax (20). besides, all the considerations leading to equation (12), as well as equation (12), still apply. this will al- ways be true if v cspktmin is greater than v cspk1 , that is if the ratio p inmax /p intmin is such that: p inmax p intmin 1.633 - v o 0.367 - v o (21) (= 4.45 for v o = 0), which includes also a class of ccm systems. in practice, the above equations apply to the large majority of common flyback designs. once the system is in standby mode, in equations (15) z e must be evaluated for fsw = f sb , becoming z e' . this will modify also p int ,p intmin and v cspkt : they all increase and become p int' ,p intmin' and v cspkt' respectively. when v cspk =v cspk2 , that is when the input power is p innw and the frequency is to be switched back to f osc , the system can be working either in dcm or ccm, depending on the f osc /f sb ratio and on v e (that is, on the input voltage). in other words, it depends on whether v cspkt' is greater or less than v cspk2 .itis possible to find that if the following condition: f osc f sb 1 2 ? 0.867 - v o 1 - v o ? v emin v e ? ? ? ? 1 + p inmax p intmin ? ? ? (22) is fulfilled, then v cspkt' >v cspk2 and the system will be working in dcm. the right side of (22), for v o = 0, is top limited at 1.87 in mcm systems. considering that in most practi- cal cases the f osc /f sb ratio will not be less than 2, it is possible to leave out the case of ccm operation. this makes things easier because there would be also a dependenceof p innw on v e . in the end, p innw will be given again by equation (13) which, rearranged more conveniently, becomes: p innw p inmax = 1 4 ? ? ? ? 0.867 - v o 1 - v o ? ? ? 2 ? ? ? ? 1 + p inmax p intmin ? ? ? 2 ? p intmin p inmax ? f sb f osc (23) AN1049 application note 6/24 the inspection of equations (15)...(23) shows that also in mcm systems the effect of the offset v o is the same as in dcm systems. furthermore, the internal thresholds v t1 and v t2 are such that a large range of applications can be covered without any external adjustment. standby function setup it is difficult to outline a general procedure for the use of the l5991's standby function because the constraints of a specific design may be of different types and are not known in advance. it is possible, however, to pro- vide some diagrams that summarize the analysis previously carried out and that can be used for reference. in figure 5 the ratio p insb /p inmax is plotted against the offset voltage on current sense v o , for different values of the parameter k m defined as: k m = p inmax p intmin (24). in figure 6, the ratio p innw /p inmax is plotted against the ratio f osc /f sb for the two ex- treme values (0 and 200 mv) considered for v o . the inspection of such diagrams shows a large influence of v o on p insb , but a much smaller influence on p innw , which depends mainly on the ratio f osc /f sb . if the values of fosc and f sb are both already fixed, there is little room for the adjustment of p innw . this is not usually a problem because there is no harmful effect if the converter is operating at f sw =f sb even when the load is not so light (e.g. 40% of the maximum load or even more). this considering, one possible step-by-step procedure could be the following: 1. check whether the flyback is dcm or mcm. to this end, from table (a1) pick up the value of v emin relevant to the specification value and calculate i ppktmin : i ppktmin = v emin z e = v emin l p ? f osc if the resulting value is greater than 1/rs then the system will be dcm, otherwise mcm. 2. calculate p inmax . if the system is dcm use the following equation: p inmax = 1 2 ? l p ? ? ? ? 1 r s ? ? ? 2 ? f osc (dcm) otherwise use: p inmax = v emin r s - v emin 2 2 ? l p ? f osc (mcm). v o [mv] k m =3 k m 1 k m = 2.5 k m =2 k m = 1.5 p in sb p in max % k m = p in max p int min 0 50 100 150 200 0 5 10 15 20 figure 5. p insb /p inmax ratio vs. dc offset on current sense. 2 2.5 3 3.5 4 4.5 5 10 20 30 40 50 q( ) , , 01z q( ) , , 0 1.5 z q( ) , , 02z q( ) , , 0 2.5 z q( ) , , 03z z k m =3 k m 1 k m = 2.5 k m =2 k m =1.5 p in nw p in max % f osc f sb v o =0 2 2.5 3 3.5 4 4.5 5 10 20 30 40 50 q( ) , , 200 1 z q( ) , , 200 1.5 z q( ) , , 200 2 z q( ) , , 200 2.5 z q( ) , , 200 3 z z k m =3 k m 1 k m = 2.5 k m =2 k m = 1.5 f osc f sb v o = 200 mv p in nw p in max % figure 6. p innw /p inmax ratio vs. f osc /f sb ratio for 0 and 200 mv dc offset on current sense. AN1049 application note 7/24 3. calculate p intmin : p intmin = v emin 2 2 ? l p ? f osc 4. calculate k m from (24). 5. in the diagrams of fig. 5, select the curve whose k m value is closest to the one calculated in the pre- vious step. then find the offset voltage v o to be applied to the current sense pin so that the standby power p insb is close to the target value. 6. select the curve whose k m value is closest to the one calculated in step 4 in either diagram of fig. 6, depending on the value of v o selected in the previous step. then find the f osc /f sb ratio that better fits the target value of p innw , consistently with the constraints imposed by the specifications. 7. calculate the new value of r s (r' s ) needed to get the same p inmax : r s ' = r s ? ( 1 - v o ) standby function and error amplifier compensation the control loop of a l5991-based flyback must be stable over a very wide range of operating condi- tions. these include the entire input voltage range and an input power going from p insb to p inmax when operating at f sw =f osc and from p inmin to p innw at f sw =f sb . moreover, the transition from standby mode to normal operation and vice versa must not have uncertainties. this requires the output of the error ampli- fier to react to frequency changes without overshoots and undershoots that exceed the other threshold, thus causing the oscillator frequency to switch back and forth between f sb and f osc . and finally, when flyback operates in ccm, its control-to-output transfer function (dv out /dv comp , where v comp is the output voltage of the error amplifier of the l5991) features the so-called rhp (right-half plane) zero, which boosts the gain like a normal zero (a zero lying on the left-half plane) but lags the phase like a pole. the rhp zero, which shifts with the duty cycle, is difficult if not impossible to compen- sate and therefore must be kept well beyond the closed-loop bandwidth. this sometimes means that the bandwidth must be narrow. from what told above, to achieve stability under all operating conditions, the error amplifier will need quite a heavy compensation, such that the overall bandwidth may be even narrower than f sb /4 f sb /5, which one could expect. as a result, the transient response of such a system will not be extremely fast. on the other hand, the applications requiring the standby function do not have such a need. 2) optimizing the design for maximum efficiency at light load start-up & self-supply circuits. usually the start-up circuit is most commonly realized with a resistor (r start ) that draws current from the rectified and filtered dc bus (fig. 7 a). this solution is cheap but not the most efficient. a reduction of the power dissipated at high mains voltage can be achieved by connecting the start-up re- sistor to the ac side of the bridge rectifier through a low-voltage diode (see fig. 7b). in both circuits, r start carries the start-up current of the controller ic in addition to the one needed to charge the supply capacitor (c supply ) up to the start-up threshold of the ic. this current must be en- sured even at the minimum line voltage (v acmin ), which imposes a limit on the maximum value of r start . in practice, however, r start will be quite lower than the maximum value, despite this increases power dissipation especially at maximum mains voltage (v acmax ). in fact, the higher r start is, the less current is available to charge c supply and therefore the longer the supply voltage takes to reach the start-up threshold (v th ) of the ic, in particular at minimum mains. to reduce this wake-up time (having fixed r start ), the supply capacitor should be as low as possible, accounting for the time necessary for the self-supply circuit to take over and sustain the operation of the ic (see fig. 8). AN1049 application note 8/24 figure 7. possible start-up circuit configurations r 8 12 l5991 va c a) start c supply 8 12 l5991 c supply vac r start 1n4148 b) vac 8 12 l5991 csupply 4 33 k w 20 v 47 k w 2m w std2n50-1 c) AN1049 application note 9/24 refer to appendix olight load losses evaluationo for the calcula- tion of the maximum r start and an estimate of power dissipation and wake-up time. the circuit of fig. 7c is active only during the start-up period, there- fore it reduces dramatically the power dissipated. once the sys- tem is running, the start-up mos is turned off and the only signifi- cant consumption is on the 2m w resistor (less than 20mw in a wide-range mains application). the components in the dashed box can be omitted, provided the supply voltage of the ic (v cc )is 18v or more, so that the gate-to- source voltage of the mos is be- low the turn-on threshold. this circuit can deliver several ma, thus the system will wake up very quickly. on the other hand, it re- quires several additional parts (mainly, a small high voltage mos) and therefore has an impact on the overall cost that needs to be evaluated by the designer. the i start of the l5991 is low enough (120 m a max.) to achieve a reasonably low consumption even with circuits a) or b), whose main merit is to be inexpensive. table 2 compares the worst case consumption of the start-up circuits of fig. 7a) and 7b), at minimum and maximum mains voltage. the table has been compiled assuming that the ic's work in a system that wakes up in 1s (@ v acmin ) and where the self-supply circuit is able to keep the system operating within 10 ms, at full load. the consumption of the gate drive (see opower mosfeto) is assumed to be 5ma and ics' supply voltage is v cc =15 v. the uc3842a needs a bigger c supply because its higher con- sumption would cause v cc to fall below v thoff before the above mentioned 10ms. table2. consumption of the start-up circuits of fig. 7 for 1s wake-up time (@ v acmin ). device c supply start-up circuit 110v 20% 220v 20% universal mains r start (k w ) p start (mw) r start (k w ) p start (mw) r start (k w ) p start (mw) min. max. min. max. min. max. l5991 33 m f a) 215 55 140 430 130 300 215 55 600 b) 55 55 130 130 105 250 55 55 590 uc3842a 47 m f a) 110 110 270 220 250 580 110 110 1170 b) 27 110 270 68 200 470 27 110 1190 as to the self-supply circuit, usually it develops the voltage v cc (obviously greater than v thoff ) by recti- fying and filtering the voltage generated by an auxiliary winding of the flyback transformer (see fig. 7). the power delivered by such circuit amounts at: p ss =( v cc + v f ) ? ( i q + i gd + i ext ) (25), v pin8 v thon v cc v thoff t voltage generated by the self-supply circuit wake-up time voltage across c supply figure 8. l5991 supply voltage at start-up. AN1049 application note 10/24 where v f is the forward drop on the rectifier, i q is the quiescent current of the ic, i gd the average current delivered to the gate of the mosfet by the driver output (see opower mosfeto) and i ext the current consumption of some other circuitry powered by the self-supply circuit. table 3. consumption of the self-supply circuit for different ic's. device i qmax p ssmax l5991 10ma (15 + 0.6)v ? (10 + 2)ma = 187 mw l5991a 10ma (9 + 0.6)v ? (10 + 2)ma = 115 mw uc3842a/b 17ma (15 + 0.6)v ? (17 + 5)ma = 343 mw table 3 summarizes a comparison concerning the power demanded to the self-supply circuit under light load conditions by different ic's. in addition to those considered in table 1 and 2, table 3 includes also the l5991a, the version of l5991 with v th = 9v (max.) and a minimum operating voltage of 8.2v (max.). the table assumes i gd =2ma for l5991, l5991a (due to their standby function) and i gd =5ma for the uc384xa/b, i ext =0, v cc =15v (9v for l5991a), v f = 0.6v and maximum i q . if the start-up circuit is (a) or (b), a low v cc will cause higher power to be dissipated in r start , but will also lead to a lower p ss . in practical cases, the contribution of v cc to p ss is prevailing thus the total power consumption p start +p ss will be lower at low v cc . if the start-up circuit is (c) a low v cc requires the use of the npn transistor and the 47 k w resistor to turn off the start-up mos, but is definitely advantageous in terms of consumption. as a result, it is advisable to keep v cc as low as possible whatever start-up circuit is used. as to this concept, the l5991a is particularly advantageous. the undervoltage lockout hysteresis, how- ever, is small (9 - 8.2 = 0.8 v) and this calls for a bigger c supply which, in turn, requires a lower r start for the same wake-up time. as a result, p start will be considerably higher. power mosfet the incidence of the mosfet on power losses at light load depends basically on the switching fre- quency. leaving out conduction losses, which can be neglected in this context, the power dissipation due to the mosfet under light load conditions consists of three contributions: 1 -turn-on losses, due to the discharge of the total capacitance of the drain node inside the mosfet. it is possible to separate two different contributions to the total drain capacitance (c drain ): c oss , the in- ternal capacitance of the mosfet, modulated by the drain voltage (manufacturers specify the value @v ds = 25v), and c dext , the external parasitic capacitance due to the transformer and to the layout of the circuit. in practice, it is possible to estimate c drain from the drain voltage oscillation occuring af- ter the secondary current has run dry in dcm operation (see fig. 9). in fact, when the transformer is discharged, the primary inductance starts resonating with c drain and the oscillation period is: t res 2 p ? ````````` l p ? c drain (26). turn-on losses depend on the input voltage in a non-monotonic way. as shown in fig. 9, the value of the drain voltage at turn-on (v don ) in dcm operation is affected by the above mentioned oscillation. an input voltage increase, despite raising the settling value of the oscillation, may lead to a lower value at turn-on because of a particular combination of t on ,t fw ,t dead and t res . 2 -turn-off losses, due to the crossing of the active region that causes a voltage-current overlapping, as shown schematically in figure 10. the fall time (t f ) of a given mosfet depends on the driver capa- bility (1.6a peak) and can be controlled with a series resistor placed between pin 10 and the gate of the mosfet. the parasitic inductances (basically, the one located between source and ground) limit the maximum di/dt rate achievable. the rate of rise of v ds depends mainly on c drain . 3 - gate drive losses, related to the charge to be delivered to the gate each time the mosfet is turned on. this charge, supplied at f sb rate, results in an equivalent dc current i gd . the parameter to be consid- ered is the total gate charge (q g ) of the device, evaluated at the gate voltage delivered by the l5991. AN1049 application note 11/24 unlike the two prior contributions, gate drive losses are not wasted inside the mosfet (except for a very small amount), but in the output stage of the l5991 and on the series gate resistor. the current i gd is seen as an additional current consumption that is added to the quiescent current of the l5991 (see equation 25). the appendix olight load losses evaluationo helps estimate the above mentioned contributions. when selecting the mosfet, the parameters to look at are the voltage rating v (br)dss , the on-state re- sistance r ds(on) , (this only as to full load considerations), the total gate charge q g and the parasitic ca- pacitances c iss ,c rss and c oss . the r ds(on) should be ojust what neededo: low enough to reduce resistive losses at full load but not too low since q g ,c iss ,c rss and c oss build up as r ds(on) decreases. it must not sound surprising to give up some efficiency points at high load in favor of an improvement at light load if that is worth it. the voltage rating of the device should be the lowest possible. in fact, for a given r ds(on) , the lower the v (br)dss is, the lower the total gate charge q g and the parasitic capacitance. a 110 v application should use a 400v device, a 220v or wide-range application a 600v device. the transformer plays a significant role as to this point (see otransformero). v ac1 t v ds t fw t off t t on t dead v ac2 v r v r t res figure 9. drain voltage waveform (dcm operation) i ppk v ds 0.9 i ppk 0.1 i ppk t f v in +v r v spike figure 10. current and voltage waveform at mosfet turn-off. AN1049 application note 12/24 last, but not least significant, the technology. a good technology device offers lower gate charge and parasitic capacitances with the same v (br)dss , and r ds(on) . transformer. the design and the assembly of the transformer plays a significant role in the process of power losses minimization. the most annoying parasitic is the so-called oleakage inductanceo, that represents the stray primary magnetic flux, modeled as an inductor in series with the primary and not coupled to the secondary. the energy stored in the leakage inductance produces an overvoltage spike on the drain of the mosfet at turn-off. an external circuit will be necessary to clamp this spike so that the voltage rat- ing of the mosfet is never exceeded. therefore, when designing and building a transformer with the aim of optimizing the efficiency of the converter at light load, the priorities are basically three: a) make the leakage inductance as low as possible. in terms of efficiency, there is a double noxious ef- fect due to the leakage inductance. it not only dumps its own energy into the clamp circuit but also delays energy transfer from primary to secondary, after mosfet turn-off, until it has run out of en- ergy. the result is that the energy stored in the mutual inductance is not completely transferred to the secondary and is partly diverted into the clamp circuit and partly dissipated in the resistance of the primary winding. this inefficiency is worsened by a light load and a high input voltage: both reduce the primary peak current and also the voltage across the leakage inductance (the leakage inductance spike) that resets the inductance itself. the lower this voltage is, the more energy transfer is delayed and the less energy is brought to the secondary. in practice, besides improving the energy transfer, a low leakage inductance will allow to lighten the action of the external clamp and/or to select a lower voltage rating mosfet. this will be beneficial to efficiency at heavy load as well. in order for a transformer to meet isolation and safety regulations, primary and secondary windings must be separated by isolation layers, thus their coupling cannot be intimate. as a result, it is not pos- sible to reduce leakage inductance below a certain extent. practically, for a well assembled trans- former, leakage inductance will be about 1 3% of the primary inductance. interleaved windings technique (putting on half the primary turns first, then all the secondaries and fi- nally the other half of the primary; see fig. 11) can reduce leakage inductance by 50%. the two pri- mary halves must be series connected, never paralleled. in general, multifilar winding technique (twisting the wire of two or more windings together) gives maximum coupling between windings. in off-line converters, however, this technique is usually appli- cable only to secondary windings to get good cross-regulation, in case of multiple output. when multi- filar winding technique is not practicable because of very different turns number (or wire size), the secondary winding with the highest output power should be wound closest to the primary; for the same power the lowest voltage should be given priority. other tricks, such as spacing windings evenly across a layer (when they do not completely fill it), or using multiple strands of wire, or keeping isolation between windings to a minimum are also effective 1/2 primary turns 1/2 primary turns secondary turns air gap on centre leg figure 11. interleaved winding technique AN1049 application note 13/24 to minimise leakage inductance. also core and coil former geometry play an important role. to achieve good coupling, windings must be long and thin, and set out in concentric fashion. therefore geometries with short and thick win- dows (such as rm, pq or pot cores) should be avoided while etd, efd, ec and the majority of e cores are good. furthermore, it is not recommended to use split coil formers, where windings are ar- ranged side by side. b) make the primary intrawinding capacitance as low as possible. this is the major component of the c dext capacitance earlier mentioned (see omosfeto). besides contributing to mosfet's power losses, it causes ringing and noise problems that may force the use of additional damping networks to comply with emc requirements. to achieve a low capacitance, always wind first the primary winding and, in particular, the half whose end is to be connected to the drain of the mosfet. in this way the second half primary has a shield- ing effect that reduces the capacitive coupling. in case of multiple layer windings, which exhibit higher capacitance, it is useful to embed one layer of isolation in between. this, however, tends to increase leakage inductance and therefore should be done with care. split coil formers are effective to this end but, as mentioned earlier, degrade leakage inductance and then should be avoided. c) make the reflected voltage low. as a rule of thumb, it should be below 60v in 110 v ac applications and less than 100v in 220 v ac or wide-range mains applications. this will reduce the voltage on the drain of the mosfet during its off-time and the losses on the resistor of the clamp network (if an rcd type is used, see oclamp networko). besides, a lower reflected voltage often leads to a primary- to-secondary turns ratio closer to 1:1. a positive side effect of that is a better magnetic coupling be- tween windings, which, in turn, helps reduce leakage inductance. on the other hand, consider that a lower reflected voltage involves higher primary peak currents at heavy load. clamp network. typically, the voltage spike due to transformer's leakage inductance is limited by an rcd clamp (see fig. 12a). its action should be very light so as to have a spike as large as possible, consistently with the need of never exceeding the voltage rating of the mosfet. this will optimize energy transfer from primary to secondary. a low leakage inductance of the transformer is, of course, extremely helpful. rcd clamps dissipate power even under no-load conditions: there is always the reflected voltage across the clamp resistor (r). to reduce clamp losses to a negligible level at light load, the use of a zener clamp (see fig. 12b) is recommended whenever possible. such a circuit gives also a well defined clamp- ing level but, on the other hand, dissipates more power at full load. its use is therefore limited to low power applications. an alternative to these solutions can be the use of a non-dissipative clamp like the lcd one shown in fig. 12c, which helps also reduce turn-off losses in the mosfet. this circuit recovers the majority of the leakage inductance energy by transferring it back onto the input voltage rail through c and d2. there is just a little power dissipation on the two diodes and the inductor. however, there is a slight increase of the conduction losses in the mosfet at heavy load and, besides, the circuit is quite expensive and not easy to optimise. r c d rcdclamp d zener clamp d z d1 lcdclamp d2 l c a) b) b) figure 12. possible clamp circuit topologies. AN1049 application note 14/24 whatever the clamp circuit topology is, the selection of the components is not trivial but needs special care to avoid annoying problems. the capacitors should be low-loss type (with polypropylene or polystyrene film dielectric) to reduce power dissipation and prevent overheating due to the high peak currents they experience. the blocking diodes must be not only very fast-recovery but also very fast-turn-on type. they should be rated for repetitive peak currents greater than ippk and their voltage rating must be adequate but not much higher than necessary. for a given diode type, the higher its breakdown voltage is, the longer its turn-on time will be. this leads to higher turn-on losses and larger overvoltage spikes, extending above the clamp level, on the mosfet's drain. the zener diode must have an adequate power handling capability in both transient and steady state op- eration. the zener voltage should be approximately 50% higher than the reflected voltage so as not to have too high power dissipation at heavy load. a transient voltage suppressor (transil) can be effectively used in place of zener diodes. table 4 lists some recommended devices available from st: bzv and 1n53xx types are zener diodes, all the others are transil. sm15txx devices are for surface mount as- semblies. table 4 - recommended st's devices for clamping power handling capability (steady state) reflected voltage 1.7w 2.0w 5.0w 6.5w 10.0w v r 50v bzw04-70 bzw06-70 bzv47c68 p6ke68a 1.5ke68a bzw50-68 sm15t68a v r 100v bzw04-128 bzw06-128 bzv47c150 p6ke150a 1.5ke150a 1n5383b bzw50-150 sm15t150a miscellaneous. there are some other hidden losses that can be significant under light load conditions and that could be worth reducing. at least, the designer should be aware of them. - dummy load. sometimes a minimum load current is required to maintain regulation and to prevent the output voltage from drifting high. a ballast resistor capable of sinking this minimum amount of current is usually placed at the output, so that the external load can be disconnected without any output volt- age drift. obviously, this resistor dissipates a constant amount of power that degrades efficiency, es- pecially at light load, and should be removed if possible or at least minimized. the frequency reduc- tion offered by the l5991 helps to this end. - feedback. the resistor divider of the feedback network (including typically an optocoupler with a volt- age reference/error amplifier like the tl431) absorbs some ma, thus representing a dummy load that adds to the actual one. if possible, the feedback network should be connected to the lowest output voltage of the converter. - residual resistive losses. although currents involved at light load are very low, some residual ori 2 o losses are still present. they are mainly located in the bridge rectifier, in the inrush current limiter, in the output steering diode and in the transformer, both as ohmic losses and radiation losses. consider also that the converter is drawing very little input (real) power but much higher (up to 4-5 times) ap- parent power and that the rms currents circulating upstream the input bulk capacitor are related to the apparent power. - case-to-heatsink parasitic capacitor. due to the capacitive coupling of the mosfet's package (typi- cally, 15-20 pf for a to220 case) to the heatsink (which is grounded for rfi reasons), current is by- passed from the drain to ground. this current does not usually generate heat but represents a dummy load. if necessary, it is possible to minimize this loss by interposing a separator, between the package and the heatsink, made up of an insulating material with a metal foil embedded in it. this halves the capacitance and therefore the current. moreover, the foil may be a point from which a little energy can be drawn for biasing some low consumption circuit. - rc damping networks. they are commonly used to damp ringings that generate emi and may be lo- cated at both the primary and the secondary side. damping is inherently dissipative, hence these rc networks should be removed. reduction of switching speed of the mosfet, careful pcb layout, ap- propriate transformer construction and selection of emi filter components may make damping unnec- essary. AN1049 application note 15/24 experimental results in order to validate the above considerations, an experimental example will be given. it concerns a 40w, wide-range mains power supply for an inkjet printer, whose design has been optimized following some of the guidelines here presented, and evaluated on the bench. fig. 13 shows the schematic with indication of the relevant parts. the 28v output powers the stepper motors while the 12v output supplies the printhead. when the printer is idle these two outputs are not loaded. the 5v section supplies the logic circuits as well as the m controller that must be operating also when the system is idle. the system operates at 100 khz at nominal load. this value is set by the parallel of the 22 k w and the 5.6 k w resistors connected at pin 2, along with the 3.3 nf capacitor placed between pin 2 and ground. when the output load is decreased so that the input power falls below about 8w, the output of the error amplifier crosses the lower threshold (v t1 ) of the internal comparator. the l5991 now disconnects inter- nally the 5.6 k w resistor, so that the capacitor is charged through the 22 k w resistor only and the oscilla- tor frequency is changed to about 20 khz. the system works in standby at 20 khz as long as the input power does not exceed about 9 w. when the load current increases and this power is exceeded, the output of the error amplifier overcomes the upper threshold (v t2 ) and the l5991 connects again the 5.6k w resistor, thus switching the oscillator fre- quency back to 100 khz. 4700pf 4kv 4700pf 4kv 4.7m stp4na60 4n35 220 2 x 330 m f 35v 1k 0.022 m f 2.7k 3.9k 28v / 0.7a gnd 470 m f 16v byw100-50 byw98-100 byw100-200 4.7m 12v / 1.5a 5v / 0.5a c02 c01 f01 ac 250v t1a 85 to 265 vac bd01 2.2 lf01 56k 10 22 13 1k 12 470pf 11 0.47 1/2 w 33 m f/25v 8 9 14 15 22 330k 47k 2 3 4 1 0.1 m f 22k 3.3 nf 16 7 330 nf 470 470pf 6 bat46 tl431 l5991 stta106 5 5.6k n1 n2 n3 n4 n aux 5.6k 5.6k 2 x 470 m f 16v 5.1k 270k 100 m f 400v bzw50-100 1n4148 56k figure 13. 40w power supply for inkjet printers. electrical schematic transformer specs. core: edt29x16x10, 3c85 material, 1.4mm air gap prim. induct: 260 m h n1: 51 t, awg26 n2: 11 t, awg25 n3: 10 t, awg20 n4: 4 t, awg25 naux: 10 t, awg32 AN1049 application note 16/24 the target was to draw from the line less than 2w over the entire input voltage range with the 28v and 12v outputs unloaded and with the minimum load (0.55 w) on the 5v section. the results of the evalu- ation are summarized in table 5. table 5. 40w power supply for inkjet printer. standby consumption. mains voltage 85vac 110vac 160vac 220vac 265vac input power 0.93w 0.97w 1.13w 1.34w 1.87w input power (*) 0.90w 0.93w 1.03w 1.14w 1.57w output power 0.55w (*) by using start-up circuit of fig. 7c. appendix flyback basics flyback's operation takes place in a two-step process. during the on time of the switch, energy is taken from the input and stored in the primary of the flyback transformer (actually, two coupled inductors). at the secondary side, the catch diode is reverse-biased, thus the load is being supplied by the energy stored in the output bulk capacitor. vout voltage reference vin clock latch r s q rs driver - + error amplifier - + 2r r 1v pwm comparator isolated feedback ip lp vcs vc v comp vc/3 is vdrain vac controller q clock v c /3 vcs=ip ? rs is vdrain vin n ? vout dcm operation q clock v c /3 vcs=ip ? rs is vdrain d ip ccm operation q clock v c /3 vcs=ip ? rs is vdrain transition figure a1. flyback topology with peak current mode control and associated waveforms AN1049 application note 17/24 when the switch turns off, the primary circuit is open and the energy stored in the primary is transferred to the secondary by magnetic coupling. the catch diode is forward-biased, and the energy is delivered to the output capacitor and to the load (recirculation). the output voltage is reflected back to the primary through the turns ratio and adds up to the input voltage (typically, the filtered rectified mains), giving ori- gin to a much higher voltage on the drain of the mosfet. flyback topology is operating in dcm (discontinuous conduction mode) when the input -or primary - current starts from zero at the beginning of a given switching cycle. this happens because the secon- dary of the transformer has discharged all the energy stored in the previous period. if this energy trans- fer is not complete, then the primary current will start from a value greater than zero at the beginning of each cycle. then the flyback is said to be operating in ccm (continuous conduction mode). dcm is characterized by currents shaped in a triangular fashion, whereas ccm features trapezoidal currents (see fig. a1). the boundary between these two types of operation depends on several parameters. some of them are structural, that is parameters that identify the flyback converter: inductance of the primary of the trans- former, transformer turns ratio and regulated output voltage. others are related to the external world and are subject to changes: input voltage and output load. the switching frequency is usually a structural pa- rameter, unless it is synchronized to an external signal. as to flyback topology operating in dcm, the relationship between the peak input current (i ppk ) and the input power (p in ) is: i ppk ( dcm ) = ```` 2 ? p in l p ? f sw (a1). where l p is the inductance of the primary of the transformer and f sw the switching frequency. the point is: in a given flyback, when operating in dcm, the peak input current depends solely on the power drawn from the input. the conduction time (t on , during which the mosfet is on) and the recirculation time (t fw , during which the mosfet is off and the catch diode is conducting) are respectively: t on = l p ? i ppk ( dcm ) v in ;t fw = l p ? i ppk ( dcm ) n ? ( v out + v f ) (a2) where v in is the dc input voltage and n the primary-to-secondary turns ratio, v out the regulated output voltage and v f the forward drop across the catch diode. the quantity n ? (v out +v f ) is the voltage reflected back to the primary during the recirculation at the secondary. in the following will be indicated with v r : v r =n ? (v out +v f ) (a3). under the assumption of dcm, the sum of t on and t fw is less than the switching period t=1 / f sw . the transition between dcm and ccm implies: t on +t fw = t (a4) and, by combining equations (a1), (a2), (a3) in (a4), it is possible to determine the otransition powero (p int ), that is the maximum input power at which a given flyback works in dcm (or rather the minimum input power at which it works in ccm) for a given input voltage (and a given switching frequency, if this can vary): p int = 1 2 ? f sw ? l p ? ? ? ? ? ? v in 1 + v in v r ? ? ? ? ? 2 (a5); AN1049 application note 18/24 obviously, dcm will take place for p in p int . this equation can be rewritten as follows: p int = v e 2 2 ? z e (a6) by defining the oequivalent input voltageo (v e ) and the oequivalent primary impedanceo (z e ): v e = v in 1 + v in v r ;z e = f sw ? l p (a7). v e is a function of v in only (see fig. a2), since the reflected voltage (v r ) is fixed. the variation of v e in its range [v emin ,v emax ], which depends on the mains voltage range, in turn defines the range of p int [p intmin ,p intmax ]. fig. a3 shows the diagram of (a6) while tab. a1 presents the ranges of v e relevant to typical mains voltage ranges, as well as the corresponding p intmax /p intmin ratios. to complete the characterization of the transition between dcm and ccm it is convenient to define the transition voltage (v et ), that is the equivalent input voltage at which the operation is on the boundary between dcm and ccm, for a given p in and a given z e : v et = ````````` ` 2 ? z e ? p in (a8). dcm will take place for v e >v et and ccm for v e < v et . in synchronized converters it is possible to define also the transition frequency (f t ), that is the switch- ing frequency at which the operation is on the boundary between dcm and ccm, for a given v e and a given p in : f t = v e 2 2 ? l p ? p in (a9). dcm will take place for f sw p intmax ( ? v et >v emax ): ccm flyback. peak current mode control basics the following relationships describing the opeako current mode control are based on the architecture shown in fig. a1 and implemented by the l5991. from the inspection of the schematic of fig. a1 it is possible to find the relationship between the peak pri- mary current (i ppk ), the peak voltage (v cspk ) on the (-) input of the pwm comparator and the output volt- age (v comp ) of the error amplifier (e/a): v comp = v c + 2 ? v f = 3 ? v cspk + 2 ? v f = 3 ? ( r s ? i ppk + v o )+ 2 ? v f (b1) where v f is the forward drop on each ozero duty cycle diodeo (0.7v typ.) and v o a dc offset voltage that may be applied on the (-) input of the pwm comparator (that is on the current sense pin of the l5991). v c , the voltage downstream the two zero duty cycle diodes (and applied on the x3 divider), despite not really available, can be considered for convenience. considering the 1v clamp on the (+) input of the current sense comparator, v c will be included between 0 and 3 v, and the useful swing of v comp between 2 ? v f and 3 + 2 ? v f volt. actually, equation (b1) neglects the so-called odelay to outputo of the pwm controller, that is the propa- gation delay of the current sense path (pwm comparator + latch + driver). during this time, the switch is still on and the input current keeps on ramping up, despite vcs has already hit the internal level on (-) input of the pwm comparator. this time lag (t delay , 70 ns typ. 100 ns max.) is compensated by the voltage loop when the system is regulating: v comp is slightly lower than the value predicted by (b1) but the phase margin of the control loop gain gets less. instead, when the error amplifier is saturated high and the pulse-by-pulse limiting is tripped, t delay causes the peak current i ppk to be larger than the expected limit 1 / r s . as illustrated in fig. b1, the effect is more pronunciated as the input voltage increases. AN1049 application note 20/24
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